1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to vertical power budgeting and shifting for three-dimensional integration.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as layer or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 or other technology, and the strata could include through-Silicon vias (TSVs) to connect from the front side to the back side of the strata or other forms. The strata could be stacked face-to-face or face-to-back where the active electronics can be on any of the “face” or “back” sides of a particular stratum.
While performance advantages have attracted attention, 3D integrated circuits are reported to be power and temperature limited due to the increased number of layers per footprint area. In a 3D stack, power dissipation per unit area increases while cooling per unit area is effectively reduced by the increased packaging density.
This becomes even more prominent in high power/density options such as processor stacking options. In a 3D stacking, high power density areas can be vertically aligned without careful optimization. The resulting power density causes power delivery and C4 current issues along the corresponding vertical columns (vertical structures, e.g., TSVs and C4 connections).
Since the limited power delivery resources are shared among strata vertically (i.e., in the form of through-Silicon vias (TSVs) and micro C4 (uC4) structures), specific management techniques are needed to address the cases where the different strata compete for the limited current and power budget resources.